It is widely known that POR circuits, typically formed on a semiconductor chip or integrated circuit (IC), initially reset the internal circuits of the chip automatically when an operating voltage is first switched on to the chip. POR circuits typically prevent invalid conditions in an electrical circuit by ensuring that the electrical circuit has sufficient power before allowing it to operate at its necessary operating conditions. In an IC, for example, a POR circuit typically may be utilized to ensure that there is a provision for adequate voltage from a power source to the chip before the chip is operationally enabled.
In operation, the POR circuit enables the chip only when the power required to adequately power the chip is known to be available from the power source and is within a predetermined or specified range. If the power requirements are inadequate or where the power to be supplied is not within the acceptable range, the typical POR circuit maintains the chip to be inoperable or operationally disabled. This disabling characteristic may be overcome in typical POR circuits once a POR circuit determines that the needed power is available, usually via a voltage “trip point” of the POR. Once a predetermined voltage is received by the POR circuit, a threshold is met and the POR circuit typically thereafter enables the operation of the chip by a signal. Conversely, a signal may also be sent based on upon a determination that there is a voltage drop below a predetermined value whereafter the chip would be disabled. As used here, the signal used to enable or disable the chip is referred to as a “power on reset signal” or “POR signal.”
FIG. 1 is a schematic representation of an exemplary POR circuit 100. The POR circuit 100 is not intended to be the only representation of a POR circuit for use with or in consideration of the present invention as POR circuit 100 is exemplary of but one type of POR circuit. POR circuit 100 includes resistors 110, 120, 130, 140, and 150 (which form a resistor ladder), capacitors 160 and 170, transistors 180 and 190, a ground path at 185, and an inverter 199. POR circuit 100 is powered by a power source which may be a power supply at 115 having a voltage supply to the circuit of VSUPPLY and which may also be the same power supply providing power to the chip (not shown) controlled by POR circuit 100.
Operationally, the resistor ladder produces a scaled version of VSUPPLY that appears on node NV at 125 which controls the voltage on the gate of transistor 180. When the scaled version of VSUPPLY reaches the threshold voltage (i.e., predetermine threshold voltage) of transistor 180, transistor 180 will turn ON. Once operational, transistor 180 pulls the input voltage to inverter 199 via node NO at 198 to ground, resulting in a logical HIGH state output 197 (e.g., POR signal) at node NOUT of the inverter 199, thereby enabling the chip (not shown) controlled by the POR circuit 100.
In this arrangement, where VSUPPLY rises from ground to its operating level (i.e., in an OFF to ON scenario), the POR circuit 100 maintains the chip as being disabled until VSUPPLY achieves a value (i.e., voltage amount) sufficient to trip transistor 180 to an ON state (i.e., trip point threshold).
Conversely, the chip controlled by POR circuit 100 is disabled when NOUT 197 is at a logical LOW, as there is no pulling of voltage across NV at 125 to the inverter 199. Instead, when VSUPPLY voltage is below the trip point threshold, transistor 180 is disabled (e.g., OFF) and resistor 150 pulls the input voltage to inverter 199 to the VSUPPLY voltage. Inverter 199 will interpret that VSUPPLY voltage is at a logical HIGH, causing a logical LOW state output at 197. The logical LOW state output at 197 serves as an active LOW reset signal (e.g., POR signal), which resets the chip and maintains it as remaining disabled.
Sensitivities to noise reduction to the POR circuit 100 are attempted to be reduced by employing capacitors 160 and 170 and transistor 190. Capacitors 160 and 170 slow down the slew rate of nodes NV and NO. The effect of the slow down of the slew rate requires that VSUPPLY achieve or exceed the trip point threshold for a predetermined period of time before the voltage on NO crosses the threshold of the inverter 199 (i.e., time counting).
Because typical ICs function over a range of power-supply voltages, the ICs may also commonly include a POR circuit that resets the IC to a known state upon application of power and holds the known state until the power supply voltages settle at or near some predetermined level. In this scenario, typically, the POR circuit is powered by the same source as the rest of the IC.
FIG. 2 is a schematic representation of an exemplary POR circuit 200 including a voltage comparator 210, a voltage divider 220 and a reference circuit 230 that provides stable reference voltages that have small variations with regard to process, supply-voltage, and temperature. An example of such a reference circuit may include a Band Gap Reference circuit, such as those discussed U.S. Pat. No. 6,489,835 to Yu et al. and U.S. Pat. No. 6,323,630 to Banba, both of which are incorporated herein by reference.
From FIG. 2, the reference circuit 230 provides a signal VSIG at 231 to the non-inverting input of comparator 210 at 211. The voltage divider 220 provides a reference voltage VREF at 221 that is a less than the supply voltage VSUPP at 216, to the inverting input of comparator 210 at 212. Comparator 210 compares the reference current signal VSIG and reference voltage VREF to generate a POR signal, PORSIG, at 240.
A problem with typical POR circuits is that POR signals may be inaccurate as trip points may vary widely due to variations in the components, manufacturing or operating environment of resident devices. In part, this issue arises as a result of economical choices in components and operational activities versus highly-tolerant elections. Another issue arising with typical POR circuits is that POR circuits may be especially susceptible to process variations and are dependent on generated signals and voltage comparisons based on voltage-centric dependencies. Often POR circuits generate PORSIG by a simple comparison of voltage values including capacitor charge voltages via basic comparator operations, which are also susceptible to wide variations. Additionally, a further limitation of typical POR circuits is that time counting is employed and power supply sources are not monitored or evaluated.
Unfortunately, these limitations have thus proven to be unavoidable challenges in the field. As can be appreciated, reliable, economical and efficient techniques for generating accurate power on reset signals for various circuit and chip applications are highly desirable.
Accordingly, what is needed is a method and apparatus for generating precise power on reset signals by relating characteristics of typical components or circuits through a novel current architecture which permits voltage threshold monitoring that is cost effective and may be readily implemented.